vhdl

4x2 Encoder in VHDL - Structural Modeling

Table of Contents

1. Project Overview
2. Theory
   • Encoder Explanation
   • Truth Table
3. VHDL Code Implementation
4. Simulation in Xilinx Vivado
   • Testbench Creation
   • Waveform Analysis
5. Images

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Project Overview

A 4x2 Encoder is a combinational circuit that encodes four input lines into a two-bit binary representation. Only one input should be high at a time.

This project implements a 4x2 Encoder using Structural Modeling in VHDL, simulates it in Xilinx Vivado, and verifies its correctness.

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Theory

Encoder Explanation

A 4x2 Encoder has:

• 4 Input lines: D(0) - D(3)
• 2 Output lines: Y(1) - Y(0)

The outputs are determined based on which input line is high.

Truth Table

D(3)	D(2)	D(1)	D(0)	Y(1)	Y(0)
0	0	0	1	0	0
0	0	1	0	0	1
0	1	0	0	1	0
1	0	0	0	1	1

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VHDL Code Implementation

The Structural Modeling approach is used to build the encoder using basic logic gates.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder_4x2 is
    Port ( D : in STD_LOGIC_VECTOR(3 downto 0);
           Y : out STD_LOGIC_VECTOR(1 downto 0)
           );
end encoder_4x2;

architecture Structural of encoder_4x2 is

begin
    Y(1) <= D(2) or D(3);
    Y(0) <= D(1) or D(3);

end Structural;

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Simulation in Xilinx Vivado

The 4x2 Encoder functionality was verified by simulating its VHDL implementation in Xilinx Vivado.

Testbench Creation

A testbench was written to apply all possible input combinations.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder_4x2_struct_tb is
end encoder_4x2_struct_tb;

architecture Behavioral of encoder_4x2_struct_tb is
    signal D : STD_LOGIC_VECTOR(3 downto 0);
    signal Y : STD_LOGIC_VECTOR(1 downto 0);
begin
    -- Instantiate UUT (Unit Under Test)
    uut: entity work.encoder_4x2 port map (D => D, Y => Y);

    process
    begin
        -- Test different inputs
        D <= "0001"; wait for 20 ns;
        D <= "0010"; wait for 20 ns;
        D <= "0100"; wait for 20 ns;
        D <= "1000"; wait for 20 ns;
        wait;
    end process;
end Behavioral;

Waveform Analysis

The simulation results confirm that the encoder correctly maps the input to the corresponding binary output.

D(3)	D(2)	D(1)	D(0)	Y(1)	Y(0)
0	0	0	1	0	0
0	0	1	0	0	1
0	1	0	0	1	0
1	0	0	0	1	1

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Images

Here are the screenshots of the 4x2 Encoder simulation results:

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Made by Swaroop Kumar Yadav

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